1. Field of the Invention
This invention relates generally to computers and data processing systems including programmable methods or procedures and more particularly to a programmable logic array based on a RAM cell coupled with an intelligent direct memory access (DMA) controller.
2. Background of the Invention
Conventional programmable logic utilizes an array of logic gates which have selectable inputs. For instance, a 20-pin programmable logic device may contain a number of 32-input AND gates. The 32 inputs generally comprise both the true and complement of logic inputs and certain feedback signals from outputs. These AND gates, in turn, feed an array of OR gates or NOR gates. Thus, if one breaks down a desired logic function into the familiar sum-of-products form (MIN TERMS) it may be implemented by selecting only the appropriate inputs to the AND gates and possibly the OR (NOR) gates. It most programmable logic devices the connections between AND and OR (NOR) gates are fixed, sacrificing some programmable logic flexibility, but keeping device complexity at a more reasonable level.
Typically, interconnections among logic elements in the array are achieved via a fusible link or non-volatile memory cell (EPROM or EEPROM). Therefore, once a logical function for a device has been decided, it is programmed and designed into a system. At that point, the logical function of the device is fixed. It is either totally incapable of being reprogrammed, or it must be removed from the system to be reprogrammed.
The foregoing illustrates limitations known to exist in present devices. Thus, it is apparent that it would be advantageous to provide an alternative directed to overcoming one or more of the limitations set forth above. Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter.